As high-resolution analog to digital converters with a simple circuit structure, time analog to digital converters, referred to as TAD converters, have been conventionally developed. Examples of the TAD converters are disclosed in U.S. Pat. No. 5,396,247 corresponding to Japanese Unexamined Patent Publication No. H05-259907.
The TAD converters of the U.S. patent publication are each composed of a plurality of digital circuits each configured to perform a particular logical function based on at least two discrete voltage levels.
Specifically, one typical example of the TAD converters includes a pulse delay circuit composed of a plurality of delay units that corresponds to a plurality of stages of delay. The delay units are connected to one another in series or in a ring-like structure.
In the TAD converter, when a pulse signal is input to one of the delay units corresponding to the first stage of delay, a pulse signal is sequentially transferred by the delay units while being delayed by the delay units in the order from the first stage of delay units toward the last stage thereof. On the other hand, an analog voltage signal as a target for A/D conversion is input to each delay unit as power supply voltage, so that the delay time of each delay unit depends on the level of the power supply voltage (the analog voltage signal) supplied to each delay unit.
Specifically, the TAD converter is designed to:
count a number of stages (pulse delay units) through which the pulse signal has passed within a predetermined sampling period during transfer; this number of pulse delay units though which the pulse signal has passed within the predetermined sampling period depends on the level of the input analog voltage signal; and
output digital data of the level of the input analog voltage signal based on the counted number of stages (pulse delay units).
Such a TAD converter requires no analog circuits that perform particular functions based on a micro analog voltage signal and include an operational amplifier, resistors, and capacitors, which are essential for conventional A/D converters. This makes it possible to easily manufacture TAD converters at low cost using only CMOS (Complementary Metal-Oxide Semiconductor) digital IC manufacturing technology.
The minimum feature size of transistors, such as the dimensions of the smallest patterns, in a CMOS process using micromachining has gradually dropped below 0.1 μm (100 nm), 90-nm, and 65-nm and now reached 45-nm. Finer design rules for CMOS processes will have progressed in the future, so that the minimum feature size of transistors is expected to be lower than 30-nm in the near the feature.
Because TAD converters are each made up of a plurality of digital circuits, such a leading-edge technology in a CMOS process can be structurally applied to the manufacture of TAD converters.
In a TAD converter manufactured using a leading-edge CMOS process, breakdown voltages of transistors decreases depending on finer design rules for CMOS processes, which causes threshold voltages of transistors to decrease. In manufacturing or designing a TAD converter, in a plurality of transistors having threshold voltages from each other, desirable ones can be selected. Note that, the lower the threshold voltage of a transistor is, the higher the switching speed of the transistor is. However, the lower the threshold voltage of a transistor is, the more a leakage current in the transistor increase when switched.
Specifically, when a leading-edge technology in a CMOS process is applied to the manufacture of a TAD converter to make the threshold voltage of transistors decrease, the delay time of each delay unit of the pulse delay circuit decreases, and digital data output from the TAD converter has a high resolution.
The reduction in the threshold voltage of transistors however may increase a leakage current in the individual transistors constituting the TAD converter, which may increase dissipation of the whole of the TAD converter.